Output details
11 - Computer Science and Informatics
Edge Hill University
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Output 0 of 0 in the submission
Output title
Simulating CPU Pipelining for Computer Architecture Teaching and Learning Support
Type
E - Conference contribution
DOI
-
Name of conference/published proceedings
Informatics Education Europe IV Conference
Volume number
-
Issue number
-
First page of article
n/a
ISSN of proceedings
-
Year of publication
2009
Number of additional authors
0
Additional information
<7> This peer-reviewed paper describes a 5-stage functional CPU pipeline simulator which is an integral part of a system simulator. It presents a set of exercises that demonstrate the technology the modern pipelines utilise to enhance CPU performance through colour-coded visualisation and animation techniques and then describes a methodology for evaluating the simulations. As a result, both the simulation exercises and the visualisations have significantly contributed to the adoption of the system simulator by tutors in several international universities as a teaching and learning resource.
Interdisciplinary
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Cross-referral requested
-
Research group
1 - Computer Assisted Teaching and Learning
Citation count
-
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
