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An ultralow-resistance ultrashallow metallic source/drain contact scheme for III-V NMOS

This is the first report of a manufacturing route for III-V MOSFETs which is compatible with silicon and meets a key resistance metric. The research results from a collaboration with the Taiwan Semiconductor Manufacturing Company (TSMC, matthias.passlack@tsmc.com), which has assigned an employee to Glasgow. Thayne has given invited conference talks on the results, including at the 2012 European Compound Semiconductor Conference as highlighted by Compound Semiconductor (http://www.compoundsemiconductor.net/csc/features-details/19735101/III-Vs-and-the-silicon-roadma.html). The advance has enabled the demonstration of the highest performance III-V MOSFETs reported so far, a "highlight paper" at the IEDM 2013 (http://www.btbmarketing.com/iedm/releases/2013_tip-sheet.pdf paper#16.1). TSMC will continue funding the research into 2015.