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Output details

13 - Electrical and Electronic Engineering, Metallurgy and Materials

University of York

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Output 11 of 85 in the submission
Article title

Architecture and FPGA Design of Dichotomous Coordinate Descent Algorithms

Type
D - Journal article
Title of journal
Ieee transactions on circuits and systems i-Regular papers
Article number
4785484
Volume number
56
Issue number
11
First page of article
2425
ISSN of journal
1549-8328
Year of publication
2009
Number of additional authors
2
Additional information

This paper contributes to practical applications of efficient linear algebra algorithms. A family of hardware architectures for solving linear systems of equations using the DCD algorithm on FPGAs are demonstrated. Examples where previously theoretical results can be efficiently implemented in practice using this technique include, multiple adaptive filters - Univ. Politeh. Bucharest, Romania (IEEE ISSCS-2011), and University of South Australia (IEEE TSP, vol.60 (12), 2012), efficient detectors - Zhengzhou University, China (J. Central South University, June 2012, vol.19 (6)), DC-DC converters – University of Newcastle (IEEE TIA, vol.47 (5), 2011, & IEEE TPE, vol.27 (11), 2012).

Interdisciplinary
-
Cross-referral requested
-
Research group
A - Communications and Signal Processing
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-