Output details
11 - Computer Science and Informatics
University of Portsmouth
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Article title
Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
Type
D - Journal article
Title of journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Article number
-
Volume number
17
Issue number
5
First page of article
709
ISSN of journal
1557-9999
Year of publication
2009
URL
-
Number of additional authors
1
Additional information
<01>This paper presents four novel area-efficient FPGA bit-parallel architectures of FIR filters that smartly support the technique of symmetric signal extension while processing finite length signals at their boundaries. This is often overlooked in hardware implementations; however, this cannot be discarded in multi-stage convolutions e.g. in sub-band coding and filter-banks. In this paper, a smart hardware solution is developed to an elementary and widely popular building block/function in DSP applications. The new architectures lead to considerable area savings e.g. 30% for 8-tap filters.
Interdisciplinary
-
Cross-referral requested
-
Research group
None
Citation count
6
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
