Output details
11 - Computer Science and Informatics
Imperial College London
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Article title
FPGA Designs with Optimized Logarithmic Arithmetic
Type
D - Journal article
Title of journal
IEEE Transactions on Computers
Article number
-
Volume number
59
Issue number
7
First page of article
1000
ISSN of journal
0018-9340
Year of publication
2010
URL
-
Number of additional authors
2
Additional information
<01>This paper describes a new family of parameterized designs for logarithmic arithmetic targeting FPGA technology. The implemented designs are significantly faster and smaller than those in comparable technologies: for QR decomposition and vector normalization, there are 73.5 percent fewer FPGA slices and 34.1 to 43.7 percent higher throughput. A paper by Mark Arnold et al published in the 2011 IEEE Symposium on Computer Arithmetic says that: “…the synthesis results from Fu et al. [12] use the block RAMs and multipliers available in large FPGAs, and are the best available synthesis benchmarks for conventional LNS…”
Interdisciplinary
-
Cross-referral requested
-
Research group
E - Programming Languages and Systems
Citation count
5
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
