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Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

<01>This paper, and the conference version in CODES+ISSS’09, present the first deadlock-free routing architecture for on-the-fly path planning and network monitoring, leading to: (1) collaboration with MIT on dynamic-programming networks for 3D VLSI system integration, partially supported by the Royal Society; (2) further investigation into the related area of deadlock detection, resulting in the paper "Run-Time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks" which received the best paper award at DATE'2011 with over 950 submissions; (3) Mak becoming Guest Editor of a Special Issue of IET Computers and Digital Techniques on Emerging On-Chip Networks and Architectures.