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Output details

11 - Computer Science and Informatics

University of Oxford

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Output title

Assume-guarantee validation for STE properties within an SVA environment

Type

E - Conference contribution

DOI

10.1109/FMCAD.2009.5351133

Name of conference/published proceedings

Proceedings of the 9th International Conference: 2009 Formal Methods in Computer-Aided Design (FMCAD 2009)

Volume number

Issue number

First page of article

108

ISSN of proceedings

Year of publication

2009

URL

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5351133

Number of additional authors

Additional information

<01>

This research brings together a distinctive mix of theory, methodology, and experimentation and a novel implementation idea, addressing a significant industrial problem: bridging the gap between formal verification and simulation for validation of microchip designs. This work has detected bugs in real designs and is widely used by execution cluster validation teams at Intel’s Israel Design Centre to improve the quality of their formal verification environments. These results are also successfully used at Intel for test-pattern generation to search for stuck-at faults. The resulting verification tool has earned an internal Intel award. (Corroboration: senior technical staff contact details on file)

Interdisciplinary

Cross-referral requested

Research group

None

Citation count

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract