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Output details

13 - Electrical and Electronic Engineering, Metallurgy and Materials

University of Bath

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Output 10 of 74 in the submission

Article title

Architecture-aware technique for mapping area-time efficient custom instructions onto FPGAs

Type

D - Journal article

DOI

10.1109/tc.2010.237

Title of journal

IEEE Transactions on Computers

Article number

Volume number

Issue number

First page of article

680

ISSN of journal

0018-9340

Year of publication

2011

URL

http://dx.doi.org/10.1109/tc.2010.237

Number of additional authors

Additional information

This paper describes a new method to improve the area-time performance of custom instruction proccessors. The value of the work is demonstrated on a wide range of benchmarks from the MiBench and MediaBench suites. The paper describes research carried out in collaboration with the Centre for High Performance Embedded Systems (CHiPES) at Nanyang Technological University, Singapore. Dr Clarke is a Founder Member of this Centre. This work led to funding from the Lee Foundation in Singapore for an extended graduate student visit to Bath resulting in three further publications.

Interdisciplinary

Cross-referral requested

Research group

A - Advanced Sensor Technologies

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract