Output details
15 - General Engineering
University of Glasgow
A low damage etching process of sub-100 nm platinum gate line for III-V metal-oxide-semiconductor field-effect transistor fabrication and the optical emission spectrometry of the inductively coupled plasma of SF6/C4F8
The paper reports the first systematic investigation by optical emission spectrometry of a low-damage, inductively coupled plasma (ICP) etching process and its physical mechanisms. This is a key process for realizing sub-100nm platinum gate III–V MOSFETs which are expected to enable ultra-fast digital applications in defence and commerce. The research was funded by the EPSRC (EP/F002610/1 - £4M) in an international collaboration with Freescale Semiconductor, USA (M.Passlack - now with TSMC, Leuven). The etching process is now available to academic and commercial users of the JWNC (www.jwnc.gla.ac.uk) and the UK National III-V Centre (www.epsrciii-vcentre.com/partners.aspx).
