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Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG Unfoldings

<01> The paper addresses resolution of encoding conflicts - an important step in asynchronous circuits synthesis. It lifts the concurrency reduction transformation to partial-order framework, proposing a novel validity condition. This allows for better conflicts visualisation. The method was implemented, and case studies demonstrate that using concurrency reduction significantly enlarges the design space and allows better exploration of speed/area trade-off. This work inspired a subsequent fully automatic approach (IEEE TVLSI publication). This paper was selected for journal publication as one of the best papers of ACSD'06. This was an important outcome of RAEng/EPSRC fellowship EP/C53400X/1 (£264K).