Output details
11 - Computer Science and Informatics
Newcastle University
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Output 0 of 0 in the submission
Article title
Synthesis of Processor Instruction Sets from High-Level ISA Specifications
Type
D - Journal article
Title of journal
IEEE Transactions on Computers
Article number
n/a
Volume number
n/a
Issue number
-
First page of article
-
ISSN of journal
1557-9956
Year of publication
2013
Number of additional authors
5
Additional information
<02> The paper introduces an approach that incorporates Event-B in a novel context (Event-B and the supporting tools were developed in the FP7 DEPLOY IP coordinated by Newcastle). The paper's main novelty is in applying an original combination of a new formalism for representing and manipulating the architectures and Event-B. Concrete models for a family of architectures with different latency, power consumption and performance characteristics were generated. This work is now taken further in the EPSRC PRiME programme grant.
Interdisciplinary
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Cross-referral requested
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Research group
C - Dependability
Citation count
-
Proposed double-weighted
No
Double-weighted statement
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Reserve for a double-weighted output
No
Non-English
No
English abstract
-
