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C-slow retimed parallel histogram architectures for consumer imaging devices

<02> Image analysis based on histograms is widespread in consumer electronics. The paper uses a formal and mathematically provable re-timing technique to design a new histogram architecture. The array designed is tested in hardware and shown to operate at 65% faster frequency than previous designs. The design can be deployed for higher throughout when dual data rate sampling techniques are used to operate on single streams of sensors. This makes the designs more convenient for interfacing with camera sensors or microprocessors in digital cameras. Potentially a huge market and widespread impact on a range of media, electronics and surveillance industries.