Output details
13 - Electrical and Electronic Engineering, Metallurgy and Materials
Queen's University Belfast
A scalable packet sorting circuit for high-speed WFQ packet scheduling
This research presents a hardware implementation of time-stamp lookup architecture for packet scheduling at 40Gb/s, outperforming contemporary industry throughput rates. It offers the highest throughput solution in comparison with current publications. Research was conducted partly in collaboration with RWTH Aachen University, Germany. The technology has been patented, entitled “Sorting Apparatus and Method” in the EU (EP20060820411, 2008) and US (8032543, 2011), and is currently exploited commercially by university spin-out company TitanIC System Ltd (C.E.O.). This work led directly to the first published fully hardware WFQ scheduler, and to additional funding leveraged in the form of an InvestNI Proof-of-Concept project.