Output details
15 - General Engineering
University of Edinburgh (joint submission with Heriot-Watt University)
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Output 0 of 0 in the submission
Article title
Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures
Type
D - Journal article
Title of journal
IEEE Transactions on Very Large Scale Integration Systems
Article number
-
Volume number
16
Issue number
12
First page of article
1596
ISSN of journal
1063-8210
Year of publication
2008
Number of additional authors
3
Additional information
This paper, arising from GR/S24053/01 (£497K), proposes a new scheme for compressing reconfiguration bits of coarse-grained dynamically reconfigurable architectures, such as the patented RICA architecture. It demonstrates a complete RICA-based processor, comparable in size to competing processors (e.g. VLIWs) with the added advantages of higher speed and lower power consumption. A patent for RICA was granted (EP1877927) and licensed to the spin-out company RICAtek Ltd (sold in 2011 to a US-based company that currently employs an eight-strong RICA development team).
Interdisciplinary
-
Cross-referral requested
-
Research group
B - Sensors, Signals & Systems
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
