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FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

<01> This paper presents the design and power modelling of fully pipelined structures for area-delay-power-efficient implementation of FIR filters. This is a follow-up work on two EPSRC completed projects. This research has secured funding from the British Council to establish links with Infocomm-Singapore, one of the top research centres in communications. With many citations and significant impact in the area of embedded signal processing, this work was the basis of subsequent invited presentation at ICCV2009 and a tutorial at ICIP2009; two prestigious IEEE conferences. Work is also based on previous results presented in top journals and conferences (TVLSI, TCAS-I, ISCAS, FPL).