Output details
13 - Electrical and Electronic Engineering, Metallurgy and Materials
Imperial College London : A - Electrical and Electronic engineering
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Output 0 of 0 in the submission
Article title
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework
Type
D - Journal article
Title of journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Article number
-
Volume number
28
Issue number
3
First page of article
305
ISSN of journal
0278-0070
Year of publication
2009
URL
-
Number of additional authors
3
Additional information
This paper showed that co-optimizing data reuse and loop parallelism can result 5-fold performance benefits for embedded systems. It was previously thought to be infeasible, due to the large design space, but this work showed that nonlinear optimization techniques could overcome this concern. The work led to the award of the Eryl Cadwaladr Davies Prize and a runner-up prize for the 2009 CPHC/BCS Distinguished Dissertation Award. This work led to a series of invited talks, and is currently being integrated into the REFLECT compiler chain used by Honeywell and others (zlatko.petrov@honeywell.com).
Interdisciplinary
-
Cross-referral requested
-
Research group
C - Circuits and Systems
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
