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13 - Electrical and Electronic Engineering, Metallurgy and Materials

University of Liverpool

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Article title

Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/Metal-Gate Structures on Silicon

Type

D - Journal article

DOI

10.1149/1.2806172

Title of journal

Journal of The Electrochemical Society

Article number

Volume number

155

Issue number

First page of article

G13

ISSN of journal

00134651

Year of publication

2008

URL

Number of additional authors

Additional information

This paper addresses the challenges to realising deposited gate-oxides for scaling CMOS Si-chips, and demonstrates that electrical passivation is a key requirement. The work was within the PULLNANO-‘Star’-IP by Academic cluster team: Liverpool/Tyndall/Chalmers/Aachen, highly recommended in the final report (http://www.high-k-gang.eu/index.php?id=11&tx_ttnews[tt_news]=6&tx_ttnews[backPid]=9&cHash=0b9b1ebb1). It led to a further EPSRC grant (EP/1012907/ £1.3M for the team; £530k Liverpool).

Interdisciplinary

Cross-referral requested

Research group

None

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract