Output details
13 - Electrical and Electronic Engineering, Metallurgy and Materials
University of Southampton
A robust high speed serial PHY architecture with feed-forward correction clock and data recovery
Significance of output:
This paper describes a new architecture and implementation for a high speed serial data interface physical layer (SATA-PHY) in nanometre CMOS. Novel compact error correction hardware compensates for tolerances and variability in high the speed analogue input circuits with minimal area and power overhead. A pipelined blind oversampling system handles spread spectrum data without tracking problems and gives a compact and low power implementation in nanometre CMOS. A US patent application (2011/0029803) has been filed, and the design is used for the hard disk interface in a family of commercial HDTV set-top box ICs (NXP/Entropic PNX8473 and derivatives).
