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Generic low-latency NoC router architecture for FPGA computing systems

New generations of FPGA chips will increasingly comprise combinations of re-configurable logic, DSP processors, RISC processors and embedded memories. As this technology advances, conventional interconnect schemes become limited by complexity and power dissipation. This paper introduces new Network-on-Chip (NoC) architectures created to directly exploit FPGA circuit characteristics. These reduce the numbers of Look-Up-Tables and registers required significantly compared with previous FPGA NoC designs with a propagation latency of only two cycles per hop. This research paves the way for the use of such router technology in future generations of FPGAs, previously not considered practical.