Output details

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

Traffic Management (TM) is essential for complex IP networks enabling QoS for latency sensitive real-time services, e.g. video conferencing, sensor networks. This paper presents a novel hardware-based TM architecture using a complex weighted fair queing, WFQ, traffic scheduler. It is the first and only reported implementation of a fully hardware WFQ integrated in a high-throughput TM supporting large number queues. The research has been in collaboration with Altera Corp. (USA). For test, validation and demonstration purpose Altera has developed dedicated TM hardware $300K. The hardware WFQ architecture has been patented and key TM components have been widely used for custom-purpose TM solution by Altera.