Output details

A highly adaptive and efficient router architecture for network-on-chip

<01> A novel router is designed, which adapts itself in terms of buffer size allocations according to the traffic rate at run time, thus utilizing the maximum available buffer resources and QoS in NoCs. The new router consumes less power which can extend battery life of the system. Moreover it uses less memory and improves the QoS which is suitable for resource hungry and heavy traffic loads applications such as multimedia. The router architecture has been implemented on FPGA and its behaviour has been evaluated by simulations for various network sizes, buffer sizes and traffic loads.