Output details
13 - Electrical and Electronic Engineering, Metallurgy and Materials
University of Liverpool
Return to search
Output 0 of 0 in the submission
Article title
Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs
Type
D - Journal article
Title of journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Article number
-
Volume number
29
Issue number
9
First page of article
1409
ISSN of journal
0278-0070
Year of publication
2010
URL
-
Number of additional authors
-
Additional information
This paper aims to reduce manufacturing test costs for energy-efficient integrated circuits, a key challenge identified in the International Technology Roadmap for Semiconductors. The work was carried out in collaboration with research centres at ARM, Duke and Southampton Universities. It was nominated for best paper award at IEEE Trans. CAD (2010-11) and led to an EPSRC grant (EP/H011420/1). Khursheed also secured second place at the Test Technology Technical Council (TTTC) best PhD award competition (ETS'100, contact: ilia.polian@uni-passau.de).
Interdisciplinary
-
Cross-referral requested
-
Research group
1 - Bio-MEMs, Organic and Silicon Electronics (BOSE)
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-