Output details
13 - Electrical and Electronic Engineering, Metallurgy and Materials
University of Liverpool
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Article title
On the nature of the interfacial layer in ultra-thin TiN/LaLuO3 gate stacks
Type
D - Journal article
Title of journal
Journal of Applied Physics
Article number
-
Volume number
112
Issue number
4
First page of article
044102
ISSN of journal
00218979
Year of publication
2012
URL
-
Number of additional authors
10
Additional information
This paper is the first detailed work on the LaLuO3/Si interface undertaken using the state-of-the-art MEIS and XPS facilities at the Daresbury Laboratory, UK. It is the culmination of 3 years cross-disciplinary research under the European NANOSIL project with ‘Network of Excellence’ partners (http://www.nanosil-noe.eu/nanosil/nanosil-partners.html), and delivers an industry-relevant gate stack solution beyond the 14 nm CMOS technology (2020). The work has been disseminated at US and European dielectric conferences (IEEE SISC’2010, INFOS’2011), an industrial JEMI UK 2011 meeting, and led to an EPSRC first grant award (EP/K018930/1) in October 2012.
Interdisciplinary
-
Cross-referral requested
-
Research group
None
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
