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Output details

11 - Computer Science and Informatics

University of Edinburgh

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Output 107 of 401 in the submission

Output title

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

Type

E - Conference contribution

DOI

10.1109/ICSAMOS.2010.5642102

Name of conference/published proceedings

International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2010)

Volume number

Issue number

First page of article

ISSN of proceedings

Year of publication

2010

URL

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5642102

Number of additional authors

Additional information

<25> Originality: This is the first paper to demonstrate speeds for cycle-accurate CPU simulation that exceed those of an equivalent hardware-based FPGA system.

Significance: High-speed CPU simulation is a critical requirement for design-space exploration and concurrent engineering of embedded systems. This paper presented a novel timing model that can be generalized for any pipelined CPU design. This technique was adopted by commercial simulators, such as those produced by Synopsys Inc.

Rigour: Extensive performance comparison against FPGA-based systems, using broad range of benchmark applications. Winner of the Best Paper award at ICSAMOS 2010, a leading international conference in embedded computing systems.

Interdisciplinary

Cross-referral requested

Research group

C - Institute for Computing Systems Architecture

Citation count

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract