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Output details

11 - Computer Science and Informatics

University of Edinburgh

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Output 130 of 401 in the submission

Output title

Efficient sequential consistency using conditional fences

Type

E - Conference contribution

DOI

10.1145/1854273.1854312

Name of conference/published proceedings

Proceedings of the 19th international conference on Parallel Architectures And Compilation Techniques (PACT '10)

Volume number

Issue number

First page of article

295

ISSN of proceedings

Year of publication

2010

URL

http://dl.acm.org/citation.cfm?doid=1854273.1854312

Number of additional authors

Additional information

<02> Originality: While conventional fences enforce memory ordering using intraprocessor delays, we propose C-Fence (conditional fence) which uses interprocessor delays.

Significance: While compiler can enforce sequential consistency by inserting memory fences, the inserted memory fences can slow down the program significantly. We propose a novel fence mechanism which significantly reduces the slowdown (43% to 12%). The paper received a best paper award at PACT 2010 (acceptance rate: 17%) and partly led to collaboration with Intel via two Intel grants. An extended version was invited to "International Journal of Parallel Programming" (http://www.springerlink.com/content/t25537x74w27k142/).

Rigour: Paper includes correctness proofs and cycle accurate simulation.

Interdisciplinary

Cross-referral requested

Research group

C - Institute for Computing Systems Architecture

Citation count

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract