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15 - General Engineering

University of Edinburgh (joint submission with Heriot-Watt University)

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Output 180 of 305 in the submission

Article title

Methodology of Statistical RTS Noise Analysis With Charge-Carrier Trapping Models

Type

D - Journal article

DOI

10.1109/TCSI.2010.2043988

Title of journal

IEEE Transactions On Circuits and Systems Part I - Regular Papers

Article number

Volume number

Issue number

First page of article

1062

ISSN of journal

1549-8328

Year of publication

2010

URL

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5444909

Number of additional authors

Additional information

This paper reports the first technique for CMOS circuit simulation that incorporates accurate, physical models of noise and mismatch in transistors with nanoscale dimensions. Since noise relates to device dimensions, designers can therefore use the smallest possible transistors with confidence, improving cost and performance. The work was funded by EP/E002005/(£624k, 2006-10), with Wolfson MicroElectronics PLC, and IBM. The method is being introduced to industrial design toolkits in several UK companies, including Wolfson (John Pennock) and IBM (Chris Cromack), via the Scottish Funding Council (“Statdes”, £194k, 2011-14, ,derek.boyd@nmi.org.uk) project. (Industrial contact emails available).

Interdisciplinary

Cross-referral requested

Research group

B - Sensors, Signals & Systems

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract