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Output details

11 - Computer Science and Informatics

University of Edinburgh

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Output 33 of 401 in the submission
Output title

A scalable architecture for maintaining packet latency measurements

Type
E - Conference contribution
Name of conference/published proceedings
Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems
Volume number
-
Issue number
-
First page of article
391
ISSN of proceedings
-
Year of publication
2012
Number of additional authors
2
Additional information

<06> Originality: First paper to enhance latency measurement granularity from per-flow to per-packet.

Significance: Our core data structure to store packet latency outperforms other solutions; it achieves two times higher storage efficiency, 7.7 times higher estimation accuracy, 1.8 times faster insert operation, and 1.4 times faster lookup operation. The data structure can be widely used for other applications in different areas that require approximated key-value storage (e.g., security applications that store inter-packet times for covert channel detection).

Rigour: Theoretical analysis was conducted to evaluate the efficacy of the proposed core data structure, followed by extensive experiments with real packet-level traces.

Interdisciplinary
-
Cross-referral requested
-
Research group
C - Institute for Computing Systems Architecture
Citation count
0
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-