Output details
11 - Computer Science and Informatics
University of Edinburgh
Efficient sequential consistency using conditional fences
<02> Originality: While conventional fences enforce memory ordering using intraprocessor delays, we propose C-Fence (conditional fence) which uses interprocessor delays.
Significance: While compiler can enforce sequential consistency by inserting memory fences, the inserted memory fences can slow down the program significantly. We propose a novel fence mechanism which significantly reduces the slowdown (43% to 12%). The paper received a best paper award at PACT 2010 (acceptance rate: 17%) and partly led to collaboration with Intel via two Intel grants. An extended version was invited to "International Journal of Parallel Programming" (http://www.springerlink.com/content/t25537x74w27k142/).
Rigour: Paper includes correctness proofs and cycle accurate simulation.