Output details
15 - General Engineering
University of Edinburgh (joint submission with Heriot-Watt University)
Article title
A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design
Type
D - Journal article
Title of journal
IEEE Journal of Solid-State Circuits
Article number
-
Volume number
48
Issue number
3
First page of article
733
ISSN of journal
0018-9200
Year of publication
2013
Number of additional authors
4
Additional information
This approach allows state-of-the-art femtoJoule per word data conversion in advanced nanometer CMOS technology at Gigasample/s rates. The novel CMOS analogue to digital converter architecture has the highest levels of time-interleaving yet achieved. The converter was supported financially by Gigle Semiconductor (£50k) for powerline modems at Gb/s data rates. Gigle were acquired by Broadcom (Keith Findlater, email available) who patented the architecture (EP 2424114 A2). First author Danesh (Seyed.Danesh@metroic.com) is now CTO of start-up company Metroic (www.metroic.com) who are licensing this IP for smart metering.
Interdisciplinary
-
Cross-referral requested
-
Research group
B - Sensors, Signals & Systems
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
