Output details

Efficient routing techniques in heterogeneous 3D Networks-on-Chip

<01> Proposes adaptive routing techniques for heterogeneous 3D NoC architectures where a combination of 2D and 3D routers is used to limit the number of vertical links. The proposed router improves the performance of NoCs up to 75% by replacing static routers, while keeping energy consumption nearly at the same level. This architecture can be applied in 3D multi-core SoCs where applications with power and timing constraints are running. The router has been implemented at RTL to evaluate the energy consumption and the routing algorithms and various 3D router arrangements have been simulated under different traffic patterns.