Output details

Single error correctable bit parallel multipliers over GF(2^m)

<01>This paper proposes a single error correction scheme, with multiple error detection capability, in circuits designed over Galois Fields (GF) for mitigating soft or transient fault related attacks. The ideas can also be used for error correction in remote and space applications and in technologies which are inherently unreliable, e.g. various nano-scale device technologies. This approach is superior to current industrial approaches, e.g. based on triple modular redundancy, in terms of hardware overheads and error correction capability. As such, this has been well received by industry and forms the basis of our proposals for commercialization endeavours.