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Derivation of reduced test vectors for bit parallel multipliers over GF(2^m)

<01>This paper presents a novel approach for optimally testing bit parallel multipliers over GF(2m), which are the critical components in cryptographic hardware, against manufacturing defects. The major impact of this approach, as evident from industrial feedback and experimentations, is that owing to the complexities of these systems, which can be 256 bits or more, existing techniques and industrial tools are not capable of handling these systems, whereas this technique optimally derives the test vectors from the algebraic properties over GF(2m), which is independent of the complexity of the circuits, and hence does not have this limitation.