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C-Testable Bit-Parallel Multipliers Over GF(2m)

<01>This paper proposes a C-testability scheme for detecting manufacturing defects in multiples over GF(2m), of any complexity, with only 8 test vectors, while mitigating side channel attacks through conventional testing mechanisms by keeping all the testing and test evaluation circuitry on chip. This is superior to existing approaches, which are incapable of handling very large bit parallel multipliers over GF(2m), commonly used in cryptographic hardware. This approach has been well received in the industrial community and has served as a catalyst for our commercialization endeavours.