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13 - Electrical and Electronic Engineering, Metallurgy and Materials

University of Liverpool

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Output 29 of 76 in the submission

Article title

Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs

Type

D - Journal article

DOI

10.1109/TCAD.2010.2059310

Title of journal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Article number

Volume number

Issue number

First page of article

1409

ISSN of journal

0278-0070

Year of publication

2010

URL

Number of additional authors

Additional information

This paper aims to reduce manufacturing test costs for energy-efficient integrated circuits, a key challenge identified in the International Technology Roadmap for Semiconductors. The work was carried out in collaboration with research centres at ARM, Duke and Southampton Universities. It was nominated for best paper award at IEEE Trans. CAD (2010-11) and led to an EPSRC grant (EP/H011420/1). Khursheed also secured second place at the Test Technology Technical Council (TTTC) best PhD award competition (ETS'100, contact: ilia.polian@uni-passau.de).

Interdisciplinary

Cross-referral requested

Research group

1 - Bio-MEMs, Organic and Silicon Electronics (BOSE)

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract