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13 - Electrical and Electronic Engineering, Metallurgy and Materials

Queen's University Belfast

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Output 9 of 133 in the submission

Article title

A scalable packet sorting circuit for high-speed WFQ packet scheduling

Type

D - Journal article

DOI

10.1109/TVLSI.2008.2000323

Title of journal

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article number

4553746

Volume number

Issue number

First page of article

781

ISSN of journal

1063-8210

Year of publication

2008

URL

Number of additional authors

Additional information

This research presents a hardware implementation of time-stamp lookup architecture for packet scheduling at 40Gb/s, outperforming contemporary industry throughput rates. It offers the highest throughput solution in comparison with current publications. Research was conducted partly in collaboration with RWTH Aachen University, Germany. The technology has been patented, entitled “Sorting Apparatus and Method” in the EU (EP20060820411, 2008) and US (8032543, 2011), and is currently exploited commercially by university spin-out company TitanIC System Ltd (C.E.O.). This work led directly to the first published fully hardware WFQ scheduler, and to additional funding leveraged in the form of an InvestNI Proof-of-Concept project.

Interdisciplinary

Cross-referral requested

Research group

D - Secure Digital Systems (SDS)

Proposed double-weighted

Double-weighted statement

Reserve for a double-weighted output

Non-English

English abstract