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13 - Electrical and Electronic Engineering, Metallurgy and Materials
University College London
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms
Collaboration (and funding) from ARM. New integrated circuit design technique to deal with a problem encountered in next generation highly-packed and energy-efficient digital integrated circuits. The new IC design techniques mitigates erroneous operation due to timing; a key problem in high speed-low power circuits. A new approach (tested analytically, algorithmically and practically) is the subject of several related ARM patents (published US-patent_12926436/ Nov.2010). The approach leads to adaptive systems operating at very low supply voltages to implement various DSP functions on silicon for use in future ARM and other digital IC designs. ARM contact Drs D. Bull and P. Whatmough.
