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Improved sub-threshold slope in short channel vertical MOSFETs using FILOX oxidation

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This paper describes work on MOS transistor designs intended for RF applications, where the short channel lengths necessary are formed by employing current flow vertically in a silicon pillar structure. The use of a novel surround gate has many advantages including offering protection to the channel region during plasma etching during the fabrication process. Experimental results show the origins of associated fabrication problems, and measurements clearly demonstrate the advantages of the new gate structure. This technique is important in enabling short channel high frequency devices to be manufactured with lower resolution lithography technology, reducing mask and equipment cost.