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Output details

13 - Electrical and Electronic Engineering, Metallurgy and Materials

University of Southampton

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Article title

Improved state integrity of flip-flops for voltage scaled retention under PVT variation

Type
D - Journal article
Title of journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Article number
-
Volume number
60
Issue number
11
First page of article
1
ISSN of journal
1057-7122
Year of publication
2013
Number of additional authors
4
Additional information

Significance of output:

Literature reports on simulations have claimed that data corruption in microprocessors can occur as a result of the fabrication process, voltage variations or temperature variations. This paper is the first to show that state integrity of microprocessor registers are indeed sensitive to such variation, based on data measured from 82 fabricated silicon chips. The significance of this work is the experimental evidence demonstrating that low-voltage embedded processors are vulnerable to failures. This research was carried out with ARM, Cambridge over a four-year period (david.flynn@arm.com). This led to the award of EPSRC Programme Grant EP/K034448/1 (£5.6M).

Interdisciplinary
-
Cross-referral requested
-
Research group
None
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-