Output details
15 - General Engineering
University of Edinburgh (joint submission with Heriot-Watt University)
Methodology of Statistical RTS Noise Analysis With Charge-Carrier Trapping Models
This paper reports the first technique for CMOS circuit simulation that incorporates accurate, physical models of noise and mismatch in transistors with nanoscale dimensions. Since noise relates to device dimensions, designers can therefore use the smallest possible transistors with confidence, improving cost and performance. The work was funded by EP/E002005/(£624k, 2006-10), with Wolfson MicroElectronics PLC, and IBM. The method is being introduced to industrial design toolkits in several UK companies, including Wolfson (John Pennock) and IBM (Chris Cromack), via the Scottish Funding Council (“Statdes”, £194k, 2011-14, ,derek.boyd@nmi.org.uk) project. (Industrial contact emails available).