Output details
11 - Computer Science and Informatics
Imperial College London
Output title
Optimizing Residue Arithmetic on FPGAs
Type
E - Conference contribution
Name of conference/published proceedings
International Conference on Field-Programmable Technology 2008
Volume number
-
Issue number
-
First page of article
41
ISSN of proceedings
-
Year of publication
2008
URL
-
Number of additional authors
2
Additional information
<01> Acceptance 22.9%/134 This paper received Best Paper Award at FPT 08. It reports a novel library generator for residue arithmetic targeting FPGAs, designed to reduce latency and area. Evidence of significance: (1) this library generator shows, for the first time, improvements of designs adopting residue arithmetic over those adopting integer arithmetic for large word-lengths; (2) the library generator approach led to the basis for compilation tools from Maxeler for their FPGA-based accelerators targeting high-performance applications; (3) the FP7 project FASTER on optimising FPGA designs by run-time reconfiguration.
Interdisciplinary
-
Cross-referral requested
-
Research group
E - Programming Languages and Systems
Citation count
2
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
