Output details

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach

<02>Paper addressing the problem of evaluating the impact of dynamic mapping heuristics on the power dissipation of Networks-on-Chip (NoCs). It proposes novel heuristics and an evaluation framework supporting detailed application modelling and co-simulation with NoC platforms, extending the state-of-the-art by accurately estimating both average and peak power. Peak power is highly relevant to industrial designs due to its impact on chip reliability, encapsulation and heat dissipation costs, but not addressed in related work because of the difficulties in modeling application-specific computation and communication behaviour (overcome in this paper). International collaborative work, led to successful EU FP7 proposal DreamCloud.