Output details

Exploring NoC-Based MPSoC Design Space with Power Estimation Models

<01>An extended version of the paper which won the best paper award at the 22nd International Symposium on Integrated Circuits and Systems Design. Pre-print had title “Using abstract power estimation models for design space exploration in NoC-based MPSoC”. (Editor suggested current title.) First attempt to use rate-based power estimation to evaluate on-chip interconnects under application-specific scenarios. Extensive validation showed a five-fold estimation time improvement over commercial register-transfer-level estimation tools and up to 50% accuracy improvement over state-of-the-art volume-based estimators. This research formed the basis for the successful EPSRC proposal LowPowNoC.