Output details
13 - Electrical and Electronic Engineering, Metallurgy and Materials
University of Southampton
Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems
Significance of output:
This international collaboration led to the first low-power VLSI design for the synchroniser and channel estimator for an IEEE 802.11a/Hyperlan compatible single-chip modem integrating novel low-power designs for system blocks and exploiting a novel power reduction strategy at system level. It resulted in two patents (WO/2004/008706, US20060146962, WO/2004/036863, US20060165187), was fabricated using IHP’s (Germany) in-house process and integrated with IHP’s single-chip 802.11a/Hyperlan modem baseband processor and has been tested in real life for communication quality and power consumption using realistic scenario. It is adopted in the book “OFDM Baseband Receiver Design for Wireless Communication”, publisher Wiley, ISBN 978-0-470-822340(HB).
