Output details
13 - Electrical and Electronic Engineering, Metallurgy and Materials
Queen's University Belfast
Article title
Design and implementation of a field programmable CRC circuit architecture
Type
D - Journal article
Title of journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Article number
5075525
Volume number
17
Issue number
8
First page of article
1142
ISSN of journal
1063-8210
Year of publication
2009
URL
-
Number of additional authors
3
Additional information
This paper proposes a new generation of a field programmable parallel cyclic redundancy check, CRC, computation architecture that can be implemented on ASIC or FPGA technology. The architecture is scalable and enables run-time programmability and supports line rates of 40 and 100Gbps. The technology is used for implementing programmable hash functions for high-speed lookup and string matching for packet classification and Deep Packet Inspection (DPI). The proposed architecture is used for many network security related packet processing circuits, including industrial DPI solutions offered by Titan IC Systems Ltd. www.titanicsystems.com.
Interdisciplinary
-
Cross-referral requested
-
Research group
D - Secure Digital Systems (SDS)
Proposed double-weighted
No
Double-weighted statement
-
Reserve for a double-weighted output
No
Non-English
No
English abstract
-
